Reliability Challenges and Measures at Architecture Level

Following Moore's Law, chip designers are pushing more and more transistors into the chips, and bringing transistor dimensions closer to the physical limits. As the chips are becoming denser and faster, the secondary effects which were negligible in the earlier technologies have started playing significant roles for the current state of the art technologies. Because of these secondary effects, chips are becoming more prone to soft and hard-errors, thus robustness of future chips is becoming more of a concern. In the beginning of VLSI era chip area was the concern for Industry and academia, by the turn of 21 century powerconsumption became an add-on concern, now experts from Industry and academia are speculating that in future reliability will play as important role as power and area is playing for the current generation. There are various levels at which reliability measures can be taken: logical level, device level, and architectural level. With chips becoming more and more complex architectural level measures are becoming quite important. This article will focus on the need of architectural level reliability improvement measures, available techniques and future requirements.